Hello "Make" aficionados:
I don't understand the word 'dependency' in the context below:
From a file called Makefile:
Code: Select all
a09: a09.c
$(CC) -o a09 $(CFLAGS) a09.c
I'm learning about 'make'
Some terms:
target: dependency
<tab> command
<tab> command
Above, the idea is to create an assembler, the target, called "a09".
The construction process depends on C language source, a09.c That file is the named dependency, right? Right!
Quite understandable, but in the line below $(CC) is a place-holder for the gcc compiler.
This is the part I don't understand. Without gcc I cannot compile (i.e. create) the assembler.
Why then, is gcc not listed as a dependency. This means, of course, the there are classes of dependency.
But I don't know about those classes!
Now, Makefile does compile the assembler, a09. What don't I understand?
собака
Also, I posted this in 'beginner' (because that's what I am). Is this the correct part of the forum for this type of "Q"?